/*-----------------------------------------------------------------------------------------------*/
/*                                                                                               */
/* Copyright(c) 2010 Nuvoton Technology Corp. All rights reserved.                               */
/*                                                                                               */
/*-----------------------------------------------------------------------------------------------*/
#ifndef __BIT_DEFINE_H__
#define __BIT_DEFINE_H__

/* 6.6 System RSTSRC register */
#define RSTS_CPU              (1<<7)
#define RSTS_MCU              (1<<5)
#define RSTS_BOD              (1<<4)
#define RSTS_LVR              (1<<3)
#define RSTS_WDT              (1<<2)
#define RSTS_PAD              (1<<1)
#define RSTS_POR              (1<<0)

/* 6.6 System IPRSTC1 registsr */
#define EBI_RST               (1<<3)
#define CPU_RST               (1<<1)
#define CHIP_RST              (1<<0)

/* 6.6 System IPRSTC2 register */
#define ADC_RST               (1<<28)
#define PWM47_RST             (1<<21)
#define PWM03_RST             (1<<20)
#define UART1_RST             (1<<17)
#define UART0_RST             (1<<16)
#define SPI1_RST              (1<<13)
#define SPI0_RST              (1<<12)
#define I2C0_RST              (1<<8)
#define TMR3_RST              (1<<5)
#define TMR2_RST              (1<<4)
#define TMR1_RST              (1<<3)
#define TMR0_RST              (1<<2)
#define GPIO_RST              (1<<1)

/* 6.6 System BODCR register */
#define LVR_EN                (1<<7)
#define BOD_OUT               (1<<6)
#define BOD_LPM               (1<<5)
#define BOD_INTF              (1<<4)
#define BOD_RSTEN             (1<<3)

#define BOD_4V5               (3<<1)
#define BOD_3V8               (2<<1)
#define BOD_2V6               (1<<1)
#define BOD_2V2               (0<<1)
#define BOD_VL                (3<<1)

#define BOD_EN                (1<<0)
							  
/* 6.6 System P0_MFP register */
#define P07_SCHMITT           (1<<23)
#define P06_SCHMITT           (1<<22)
#define P05_SCHMITT           (1<<21)
#define P04_SCHMITT           (1<<20)
#define P03_SCHMITT           (1<<19)
#define P02_SCHMITT           (1<<18)
#define P01_SCHMITT           (1<<17)
#define P00_SCHMITT           (1<<16)
#define P07_AD7_SPI1CLK       ((1<<15)|(1<<7))
#define P07                   ((0<<15)|(0<<7))
#define AD7                   ((0<<15)|(1<<7))
#define SPI1CLK               ((1<<15)|(0<<7))
#define P06_AD6_SPI1MISO      ((1<<14)|(1<<6))
#define P06                   ((0<<14)|(0<<6))
#define AD6                   ((0<<14)|(1<<6))
#define SPI1MISO							((1<<14)|(0<<6))
#define P05_AD5_SPI1MOSI      ((1<<13)|(1<<5))
#define P05                   ((0<<13)|(0<<5))
#define AD5                   ((0<<13)|(1<<5))
#define SPI1MOSI							((1<<13)|(0<<5))
#define P04_AD4_SPI1SS        ((1<<12)|(1<<4))
#define P04                   ((0<<12)|(0<<4))
#define AD4                   ((0<<12)|(1<<4))
#define SPI1SS                ((1<<12)|(0<<4))
#define P03_AD3_RTS0          ((1<<11)|(1<<3))
#define P03                   ((0<<11)|(0<<3))
#define AD3                   ((0<<11)|(1<<3))
#define RTS0                  ((1<<11)|(0<<3))
#define P02_AD2_CTS0          ((1<<10)|(1<<2))
#define P02                   ((0<<10)|(0<<2))
#define AD2                   ((0<<10)|(1<<2))
#define CTS0                  ((1<<10)|(0<<2))
#define P01_AD1_RTS1          ((1<<9)|(1<<1))
#define P01                   ((0<<9)|(0<<1))
#define AD1                   ((0<<9)|(1<<1))
#define RTS1                  ((1<<9)|(0<<1))
#define P00_AD0_CTS1          ((1<<8)|(1))
#define P00                   ((0<<8)|(0))
#define AD0                   ((0<<8)|(1))
#define CTS1                  ((1<<8)|(0))
                                                
/* 6.6 System P1_MFP register */
#define P17_SCHMITT           (1<<23)
#define P16_SCHMITT           (1<<22)
#define P15_SCHMITT           (1<<21)
#define P14_SCHMITT           (1<<20)
#define P13_SCHMITT           (1<<19)
#define P12_SCHMITT           (1<<18)
#define P11_SCHMITT           (1<<17)
#define P10_SCHMITT           (1<<16)
#define P17_AIN7_SPI0CLK      ((1<<15)|(1<<7))
#define P17                   ((0<<15)|(0<<7))
#define AIN7                  ((0<<15)|(1<<7))
#define SPI0CLK               ((1<<15)|(0<<7))
#define P16_AIN6_SPI0MISO     ((1<<14)|(1<<6))
#define P16                   ((0<<14)|(0<<6))
#define AIN6                  ((0<<14)|(1<<6))
#define SPI0MISO              ((1<<14)|(0<<6))
#define P15_AIN5_SPI0MOSI     ((1<<13)|(1<<5))
#define ACMP0_P			     ((1<<13)|(1<<5))
#define P15                   ((0<<13)|(0<<5))
#define AIN5                  ((0<<13)|(1<<5))
#define SPI0MOSI              ((1<<13)|(0<<5))
#define P14_AIN4_SPI0SS       ((1<<12)|(1<<4))
#define ACMP0_N      		 ((1<<12)|(1<<4))
#define P14                   ((0<<12)|(0<<4))
#define AIN4                  ((0<<12)|(1<<4))
#define SPI0SS                ((1<<12)|(0<<4))
#define P13_AIN3_TXD1         ((1<<11)|(1<<3))
#define P13                   ((0<<11)|(0<<3))
#define AIN3                  ((0<<11)|(1<<3))
#define TXD1                  ((1<<11)|(0<<3))
#define P12_AIN2_RXD1         ((1<<10)|(1<<2))
#define P12                   ((0<<10)|(0<<2))
#define AIN2                  ((0<<10)|(1<<2))
#define RXD1                  ((1<<10)|(0<<2))
#define P11_AIN1_T3           ((1<<9)|(1<<1))
#define P11                   ((0<<9)|(0<<1))
#define AIN1                  ((0<<9)|(1<<1))
#define T3                    ((1<<9)|(0<<1))
#define P10_AIN0_T2           ((1<<8)|(1))
#define P10                   ((0<<8)|(0))
#define AIN0                  ((0<<8)|(1))
#define T2                    ((1<<8)|(0))

/* 6.6 System P2_MFP register */
#define P27_SCHMITT           (1<<23)
#define P26_SCHMITT           (1<<22)
#define P25_SCHMITT           (1<<21)
#define P24_SCHMITT           (1<<20)
#define P23_SCHMITT           (1<<19)
#define P22_SCHMITT           (1<<18)
#define P21_SCHMITT           (1<<17)
#define P20_SCHMITT           (1<<16)
#define P27_AD15_PWM7         ((1<<15)|(1<<7))
#define P27                   ((0<<15)|(0<<7))
#define AD15                  ((0<<15)|(1<<7))
#define PWM7                  ((1<<15)|(0<<7))
#define P26_AD14_PWM6         ((1<<14)|(1<<6))
#define P26                   ((0<<14)|(0<<6))
#define AD14                  ((0<<14)|(1<<6))
#define PWM6                  ((1<<14)|(0<<6))
#define P25_AD13_PWM5         ((1<<13)|(1<<5))
#define P25                   ((0<<13)|(0<<5))
#define AD13                  ((0<<13)|(1<<5))
#define PWM5                  ((1<<13)|(0<<5))
#define P24_AD12_PWM4         ((1<<12)|(1<<4))
#define P24                   ((0<<12)|(0<<4))
#define AD12                  ((0<<12)|(1<<4))
#define PWM4                  ((1<<12)|(0<<4))
#define P23_AD11_PWM3         ((1<<11)|(1<<3))
#define P23                   ((0<<11)|(0<<3))
#define AD11                  ((0<<11)|(1<<3))
#define PWM3                  ((1<<11)|(0<<3))
#define P22_AD10_PWM2         ((1<<10)|(1<<2))
#define P22                   ((0<<10)|(0<<2))
#define AD10                  ((0<<10)|(1<<2))
#define PWM2                  ((1<<10)|(0<<2))
#define P21_AD9_PWM1          ((1<<9)|(1<<1))
#define P21                   ((0<<9)|(0<<1))
#define AD9                   ((0<<9)|(1<<1))
#define PWM1                  ((1<<9)|(0<<1))
#define P20_AD8_PWM0          ((1<<8)|(1))
#define P20                   ((0<<8)|(0))
#define AD8                   ((0<<8)|(1))
#define PWM0                  ((1<<8)|(0))

/* 6.6 System P3_MFP register */
#define P37_SCHMITT           (1<<23)
#define P36_SCHMITT           (1<<22)
#define P35_SCHMITT           (1<<21)
#define P34_SCHMITT           (1<<20)
#define P33_SCHMITT           (1<<19)
#define P32_SCHMITT           (1<<18)
#define P31_SCHMITT           (1<<17)
#define P30_SCHMITT           (1<<16)
#define P37_RD                ((1<<15)|(1<<7))
#define P37                   ((0<<15)|(0<<7))
#define RD                    ((0<<15)|(1<<7))
#define P36_WR_CKO            ((1<<14)|(1<<6))
#define ACMP0_O	            ((1<<14)|(1<<6))
#define P36                   ((0<<14)|(0<<6))
#define WR                    ((0<<14)|(1<<6))
#define CKO                   ((1<<14)|(0<<6))
#define P35_T1_I2CSCL         ((1<<13)|(1<<5))
#define P35                   ((0<<13)|(0<<5))
#define T1                    ((0<<13)|(1<<5))
#define I2CSCL                ((1<<13)|(0<<5))
#define P34_T0_I2CSDA         ((1<<12)|(1<<4))
#define P34                   ((0<<12)|(0<<4))
#define T0                    ((0<<12)|(1<<4))
#define I2CSDA                ((1<<12)|(0<<4))
#define P33_EINT1_MCLK        ((1<<11)|(1<<3))
#define P33                   ((0<<11)|(0<<3))
#define EINT1                 ((0<<11)|(1<<3))
#define MCLK                  ((1<<11)|(0<<3))
#define P32_EINT0             ((1<<10)|(1<<2))
#define P32                   ((0<<10)|(0<<2))
#define EINT0                 ((0<<10)|(1<<2))
#define P31_TXD0              ((1<<9)|(1<<1))
#define P31                   ((0<<9)|(0<<1))
#define TXD0                  ((0<<9)|(1<<1))
#define P30_RXD0              ((1<<8)|(1))
#define P30                   ((0<<8)|(0))
#define RXD0                  ((0<<8)|(1))



#define P32_MFSEL       			((1<<10)|(1<<2))
#define P32_T0EX							((1<<10)|(0<<2))
#define MODE_CAP_EN						(1<<8)
#define TCDB_EN								(1<<7)
#define TEXDB_EN							(1<<6)
#define TEXI_EN								(1<<5)
#define                     TEX_EN								(1<<3)
#define TMR_CNT_RST					  (1<<4)
#define TMR_CAP								~(1<<4)
#define TMR_CAP1								(1<<4)

#define TEX_EDGE_F							(0<<1)
#define TEX_EDGE_R							(1<<1)
#define TEX_EDGE_BOTH						(2<<1)
#define TEX_EDGE							  (3<<1)

#define TEX_IF								(1)

/* 6.6 System P4_MFP register */

#define P41_MFSEL       			((1<<9)|(1<<1)) 
#define P41_T3EX							((1<<9)|(0<<1))

#define P47_SCHMITT           (1<<23)
#define P46_SCHMITT           (1<<22)
#define P45_SCHMITT           (1<<21)
#define P44_SCHMITT           (1<<20)
#define P43_SCHMITT           (1<<19)
#define P42_SCHMITT           (1<<18)
#define P41_SCHMITT           (1<<17)
#define P40_SCHMITT           (1<<16)
#define P47_ICE_DAT           ((1<<15)|(1<<7))
#define P47                   ((0<<15)|(0<<7))
#define ICE_DAT               ((0<<15)|(1<<7))
#define P46_ICE_CLK           ((1<<14)|(1<<6))
#define P46                   ((0<<14)|(0<<6))
#define ICE_CLK               ((0<<14)|(1<<6))
#define P45_ALE               ((1<<13)|(1<<5))
#define P45                   ((0<<13)|(0<<5))
#define ALE                   ((0<<13)|(1<<5))
#define P44_CS                ((1<<12)|(1<<4))
#define P44                   ((0<<12)|(0<<4))
#define CS                    ((0<<12)|(1<<4))
#define P43                   ((0<<11)|(0<<3))
#define P42                   ((0<<10)|(0<<2))
#define P41                   ((0<<9)|(0<<1))
#define P40                   ((0<<8)|(0))

/* 6.7 System SYST_CSR register */
#define COUNTFLAG             (1<<16)
#define CLKSRC_CORE           (1<<2)
#define CLKSRC_EXT            ~(1<<2)
#define TICKINT_EN            (1<<1)
#define ENABLE                (1<<0)

/* 6.8 System NVIC_ISER register */
/* 6.8 System NVIC_ICER register */
/* 6.8 System NVIC_ISPR register */
/* 6.8 System NVIC_ICPR register */
#define ADC_INT               (1<<29)
#define PWRWU_INT             (1<<28)
#define ACMP23_INT			  (1<<26)
#define ACMP01_INT			  (1<<25)
#define I2C0_INT              (1<<18)
#define SPI1_INT              (1<<15)
#define SPI0_INT              (1<<14)
#define UART1_INT             (1<<13)
#define UART0_INT             (1<<12)
#define TMR3_INT              (1<<11)
#define TMR2_INT              (1<<10)
#define TMR1_INT              (1<<9)
#define TMR0_INT              (1<<8)
#define PWMB_INT              (1<<7)
#define PWMA_INT              (1<<6)
#define GP234_INT             (1<<5)
#define GP01_INT              (1<<4)
#define EXT_INT1              (1<<3)
#define EXT_INT0              (1<<2)
#define WDT_INT               (1<<1)
#define BOD_OUT_INT           (1<<0)

/* 6.8 System NVIC_IPR7 register */ 
#define ADC_PRI0              (0<<14)	
#define ADC_PRI1              (1<<14)
#define ADC_PRI2              (2<<14)
#define ADC_PRI3              (3<<14)
#define ADC_PRI               (3<<14)

#define PWRWU_PRI0            (0<<6)	
#define PWRWU_PRI1            (1<<6)
#define PWRWU_PRI2            (2<<6)
#define PWRWU_PRI3            (3<<6)
#define PWRWU_PRI             (3<<6)

/* 6.8 System NVIC_IPR4 register */ 
#define I2C0_PRI0             (0<<22)	
#define I2C0_PRI1             (1<<22)
#define I2C0_PRI2             (2<<22)
#define I2C0_PRI3             (3<<22)
#define I2C0_PRI              (3<<22)

/* 6.8 System NVIC_IPR3 register */ 
#define SPI1_PRI0             (0<<30)	
#define SPI1_PRI1             (1<<30)
#define SPI1_PRI2             (2<<30)
#define SPI1_PRI3             ((uint32_t)3<<30)
#define SPI1_PRI              ((uint32_t)3<<30)

#define SPI0_PRI0             (0<<22)	
#define SPI0_PRI1             (1<<22)
#define SPI0_PRI2             (2<<22)
#define SPI0_PRI3             (3<<22)
#define SPI0_PRI              (3<<22)

#define UART1_PRI0            (0<<14)	
#define UART1_PRI1            (1<<14)
#define UART1_PRI2            (2<<14)
#define UART1_PRI3            (3<<14)
#define UART1_PRI             (3<<14)

#define UART0_PRI0            (0<<6)	
#define UART0_PRI1            (1<<6)
#define UART0_PRI2            (2<<6)
#define UART0_PRI3            (3<<6)
#define UART0_PRI             (3<<6)

/* 6.8 System NVIC_IPR2 register */ 
#define TMR3_PRI0             (0<<30)	
#define TMR3_PRI1             (1<<30)
#define TMR3_PRI2             (2<<30)
#define TMR3_PRI3             ((uint32_t)3<<30)
#define TMR3_PRI              ((uint32_t)3<<30)

#define TMR2_PRI0             (0<<22)	
#define TMR2_PRI1             (1<<22)
#define TMR2_PRI2             (2<<22)
#define TMR2_PRI3             (3<<22)
#define TMR2_PRI              (3<<22)

#define TMR1_PRI0             (0<<14)	
#define TMR1_PRI1             (1<<14)
#define TMR1_PRI2             (2<<14)
#define TMR1_PRI3             (3<<14)
#define TMR1_PRI              (3<<14)

#define TMR0_PRI0             (0<<6)	
#define TMR0_PRI1             (1<<6)
#define TMR0_PRI2             (2<<6)
#define TMR0_PRI3             (3<<6)
#define TMR0_PRI              (3<<6)

/* 6.8 System NVIC_IPR1 register */ 
#define PWMB_PRI0             (0<<30)	
#define PWMB_PRI1             (1<<30)
#define PWMB_PRI2             (2<<30)
#define PWMB_PRI3             ((uint32_t)3<<30)
#define PWMB_PRI              ((uint32_t)3<<30)

#define PWMA_PRI0             (0<<22)	
#define PWMA_PRI1             (1<<22)
#define PWMA_PRI2             (2<<22)
#define PWMA_PRI3             (3<<22)
#define PWMA_PRI              (3<<22)

#define GP234_PRI0            (0<<14)	
#define GP234_PRI1            (1<<14)
#define GP234_PRI2            (2<<14)
#define GP234_PRI3            (3<<14)
#define GP234_PRI             (3<<14)

#define GP01_PRI0             (0<<6)	
#define GP01_PRI1             (1<<6)
#define GP01_PRI2             (2<<6)
#define GP01_PRI3             (3<<6)
#define GP01_PRI              (3<<6)

/* 6.8 System NVIC_IPR0 register */ 
#define EINT1_PRI0            (0<<30)	
#define EINT1_PRI1            (1<<30)
#define EINT1_PRI2            (2<<30)
#define EINT1_PRI3            ((uint32_t)3<<30)
#define EINT1_PRI             ((uint32_t)3<<30)

#define EINT0_PRI0            (0<<22)	
#define EINT0_PRI1            (1<<22)
#define EINT0_PRI2            (2<<22)
#define EINT0_PRI3            (3<<22)
#define EINT0_PRI             (3<<22)

#define WDT_PRI0              (0<<14)	
#define WDT_PRI1              (1<<14)
#define WDT_PRI2              (2<<14)
#define WDT_PRI3              (3<<14)
#define WDT_PRI               (3<<14)

#define BOD_OUT_PRI0          (0<<6)	
#define BOD_OUT_PRI1          (1<<6)
#define BOD_OUT_PRI2          (2<<6)
#define BOD_OUT_PRI3          (3<<6)
#define BOD_OUT_PRI           (3<<6)

/* 6.9 System ICSR register */ 
#define NMIPENDSET            ((uint32_t)1<<31)
#define PENDSVSET             (1<<28)
#define PENDSVCLR             (1<<27)
#define PENDSTSET             (1<<26)
#define PENDSTCLR             (1<<25)
#define ISRPREEMPT            (1<<23)
#define ISRPENDING            (1<<22)

/* 6.9 System SCR register */
#define SEVONPEND             (1<<4)
#define SLEEPDEEP             (1<<2)
#define SLEEPONEXIT           (1<<1)

/* 6.9 System SHPR2 register */ 
#define	SVC_PRI0              (0<<30)
#define	SVC_PRI1              (1<<30)
#define	SVC_PRI2              (2<<30)
#define	SVC_PRI3              ((uint32_t)3<<30)
#define	SVC_PRI               ((uint32_t)3<<30)

/* 6.9 System SHPR3 register */ 
#define	ST_PRI0               (0<<30)
#define	ST_PRI1               (1<<30)
#define	ST_PRI2               (2<<30)
#define	ST_PRI3               ((uint32_t)3<<30)
#define	ST_PRI                ((uint32_t)3<<30)

#define	PENDSV_PRI0           (0<<22)
#define	PENDSV_PRI1           (1<<22)
#define	PENDSV_PRI2           (2<<22)
#define	PENDSV_PRI3           (3<<22)
#define	PENDSV_PRI            (3<<22)

/* 7. Clock PWRCON register */
#define PD_WAIT_CPU           (1<<8)
#define PWR_DOWN_EN           (1<<7)
#define PD_WU_STS             (1<<6)
#define PD_WU_IE              (1<<5)
#define WU_DLY                (1<<4)
#define OSC10K_EN             (1<<3)
#define OSC22M_EN             (1<<2)
#define XTL12M_EN             (1<<0)

/* 7. Clock AHBCLK register */
#define EBI_CLKEN             (1<<3)
#define ISP_CLKEN             (1<<2)

/* 7. Clock APBCLK register */
#define ACMP23_CLKEN			(1<<31)
#define ACMP01_CLKEN			(1<<30)
#define ADC_CLKEN             (1<<28)
#define PWM67_CLKEN           (1<<23)
#define PWM45_CLKEN           (1<<22)
#define PWM23_CLKEN           (1<<21)
#define PWM01_CLKEN           (1<<20)
#define UART1_CLKEN           (1<<17)
#define UART0_CLKEN           (1<<16)
#define SPI1_CLKEN            (1<<13)
#define SPI0_CLKEN            (1<<12)
#define I2C0_CLKEN            (1<<8)
#define FDIV_CLKEN            (1<<6)
#define TMR3_CLKEN            (1<<5)
#define TMR2_CLKEN            (1<<4)
#define TMR1_CLKEN            (1<<3)
#define TMR0_CLKEN            (1<<2)
#define WDT_CLKEN             (1<<0)

/* 7. Clock CLKSTATUS register */
#define CLK_SW_FAIL           (1<<7)
#define OSC22M_STB            (1<<4)
#define OSC10K_STB            (1<<3)
#define PLL_STB               (1<<2)
#define XTL12M_STB            (1<<0)

/* 7. Clock CLKSEL0 register */
#define STCLK_12M             (0<<3)
#define STCLK_12M_2           (2<<3)
#define STCLK_HCLK_2          (3<<3)
#define STCLK_22M_2           (4<<3)
#define STCLK                 (7<<3)

#define HCLK_12M              (0)
#define HCLK_PLL              (2)
#define HCLK_10K              (3)
#define HCLK_22M              (7)
#define	HCLK                  (7)

/* 7. Clock CLKSEL1 register */
#define PWM23_12M             (0<<30)
#define PWM23_HCLK            (2<<30)
#define PWM23_22M             ((uint32_t)3<<30)
#define PWM23_CLK             ((uint32_t)3<<30)

#define PWM01_12M             (0<<28)
#define PWM01_HCLK            (2<<28)
#define PWM01_22M             (3<<28)
#define PWM01_CLK             (3<<28)

#define UART_12M              (0<<24)
#define UART_PLL              (1<<24)
#define UART_22M              (3<<24)
#define UART_CLK              (3<<24)

#define TM3_12M               (0<<20)
#define TM3_HCLK              (2<<20)
#define TM3_EXT               (3<<20)
#define TM3_22M               (4<<20)
#define TM3_CLK               (7<<20)

#define TM2_12M               (0<<16)
#define TM2_HCLK              (2<<16)
#define TM2_EXT               (3<<16)
#define TM2_22M               (4<<16)
#define TM2_CLK               (7<<16)

#define TM1_12M               (0<<12)
#define TM1_HCLK              (2<<12)
#define TM1_EXT               (3<<12)
#define TM1_22M               (4<<12)
#define TM1_CLK               (7<<12)

#define TM0_12M               (0<<8)
#define TM0_HCLK              (2<<8)
#define TM0_EXT               (3<<8)
#define TM0_22M               (4<<8)
#define TM0_CLK               (7<<8)

#define ADC_12M               (0<<2)
#define ADC_PLL               (1<<2)
#define ADC_22M               (2<<2)
#define ADC_CLK               (3<<2)

#define WDT_12M               (0)
#define WDT_HCLK_2048         (2)
#define WDT_10K               (3)
#define WDT_CLK               (3)

/* 7. Clock CLKSEL2 register */
#define PWM67_12M             (0<<6)
#define PWM67_HCLK            (2<<6)
#define PWM67_22M             (3<<6)
#define PWM67_CLK             (3<<6)

#define PWM45_12M             (0<<4)
#define PWM45_HCLK            (2<<4)
#define PWM45_22M             (3<<4)
#define PWM45_CLK             (3<<4)

#define FRQDIV_12M            (0<<2)
#define FRQDIV_HCLK           (2<<2)
#define FRQDIV_22M            (3<<2)
#define FRQDIV_CLK            (3<<2)

/* 7. Clock PLLCON register */
#define PLL_22M               (1<<19)
#define PLL_12M               ~(1<<19)
#define PLL_OE                (1<<18)
#define PLL_BP                (1<<17)
#define PLL_PD                (1<<16)

/* 7. Clock FRQDIV register */
#define FDIV_EN               (1<<4)

/* 8. GPIO Px_PMD register */
#define Px7_IN                (0<<14)
#define Px7_OUT	              (1<<14)
#define Px7_OD                (2<<14)
#define Px7_QB                (3<<14)
#define Px7_PMD               (3<<14)

#define Px6_IN                (0<<12)
#define Px6_OUT               (1<<12)
#define Px6_OD                (2<<12)
#define Px6_QB                (3<<12)
#define Px6_PMD               (3<<12)

#define Px5_IN                (0<<10)
#define Px5_OUT               (1<<10)
#define Px5_OD                (2<<10)
#define Px5_QB                (3<<10)
#define Px5_PMD               (3<<10)

#define Px4_IN                (0<<8)
#define Px4_OUT               (1<<8)
#define Px4_OD                (2<<8)
#define Px4_QB                (3<<8)
#define Px4_PMD               (3<<8)

#define Px3_IN                (0<<6)
#define Px3_OUT               (1<<6)
#define Px3_OD                (2<<6)
#define Px3_QB                (3<<6)
#define Px3_PMD               (3<<6)

#define Px2_IN                (0<<4)
#define Px2_OUT               (1<<4)
#define Px2_OD                (2<<4)
#define Px2_QB                (3<<4)
#define Px2_PMD               (3<<4)

#define Px1_IN                (0<<2)
#define Px1_OUT               (1<<2)
#define Px1_OD                (2<<2)
#define Px1_QB                (3<<2)
#define Px1_PMD               (3<<2)

#define Px0_IN                (0)
#define Px0_OUT               (1)
#define Px0_OD                (2)
#define Px0_QB                (3)
#define Px0_PMD               (3)

/* 8. GPIO Px_OFFD register */
#define OFFD7                 (1<<23)
#define OFFD6                 (1<<22)
#define OFFD5                 (1<<21)
#define OFFD4                 (1<<20)
#define OFFD3                 (1<<19)
#define OFFD2                 (1<<18)
#define OFFD1                 (1<<17)
#define OFFD0                 (1<<16)

/* 8. GPIO Px_DMASK register */
#define DMASK7                (1<<7)
#define DMASK6                (1<<6)
#define DMASK5                (1<<5)
#define DMASK4                (1<<4)
#define DMASK3                (1<<3)
#define DMASK2                (1<<2)
#define DMASK1                (1<<1)
#define DMASK0                (1<<0)

/* 8. GPIO Px_DBEN register */
#define DBEN7                 (1<<7)
#define DBEN6                 (1<<6)
#define DBEN5                 (1<<5)
#define DBEN4                 (1<<4)
#define DBEN3                 (1<<3)
#define DBEN2                 (1<<2)
#define DBEN1                 (1<<1)
#define DBEN0                 (1<<0)

/* 8. GPIO Px_IMD register */
#define IMD7_LEV              (1<<7)
#define IMD7_EDG              ~(1<<7)

#define IMD6_LEV              (1<<6)
#define IMD6_EDG              ~(1<<6)

#define IMD5_LEV              (1<<5)
#define IMD5_EDG              ~(1<<5)

#define IMD4_LEV              (1<<4)
#define IMD4_EDG              ~(1<<4)

#define IMD3_LEV              (1<<3)
#define IMD3_EDG              ~(1<<3)

#define IMD2_LEV              (1<<2)
#define IMD2_EDG              ~(1<<2)

#define IMD1_LEV              (1<<1)
#define IMD1_EDG              ~(1<<1)

#define IMD0_LEV              (1<<0)
#define IMD0_EDG              ~(1<<0)

/* 8. GPIO Px_IEN register */
#define IR_EN7                (1<<23)
#define IR_EN6                (1<<22)
#define IR_EN5                (1<<21)
#define IR_EN4                (1<<20)
#define IR_EN3                (1<<19)
#define IR_EN2                (1<<18)
#define IR_EN1                (1<<17)
#define IR_EN0                (1<<16)
#define IF_EN7                (1<<7)
#define IF_EN6                (1<<6)
#define IF_EN5                (1<<5)
#define IF_EN4                (1<<4)
#define IF_EN3                (1<<3)
#define IF_EN2                (1<<2)
#define IF_EN1                (1<<1)
#define IF_EN0                (1<<0)

/* 8. GPIO DBNCECON register */
#define ICLK_ON               (1<<5)
#define DBCLK_10K             (1<<4)
#define DBCLK_HCLK            ~(1<<4)

#define SMP_1CK               (0)
#define SMP_2CK               (1)
#define SMP_4CK               (2)
#define SMP_8CK               (3)
#define SMP_16CK              (4)
#define SMP_32CK              (5)
#define SMP_64CK              (6)
#define SMP_128CK             (7)
#define SMP_256CK             (8)
#define SMP_512CK             (9)
#define SMP_1024CK            (10)
#define SMP_2048CK            (11)
#define SMP_4096CK            (12)
#define SMP_8192CK            (13)
#define SMP_16384CK           (14)
#define SMP_32768CK           (15)
#define SMP_CYCLE             (15)

/* 9. I2C I2CON register */
#define EI                    (1<<7)
#define ENSI                  (1<<6)
#define STA                   (1<<5)
#define STO                   (1<<4)
#define SI                    (1<<3)
#define AA                    (1<<2)

/* 9. I2C I2TOC register */
#define I2C_ENTI              (1<<2)
#define DIV4_EN               (1<<1)
#define I2C_TOF               (1<<0)

/* 9. I2C I2CADDR register */
#define GC_EN                 (1<<0)

/* 10. PWM CSR03 register */
#define CSR3_CLK_2            (0<<12)
#define CSR3_CLK_4            (1<<12)
#define CSR3_CLK_8            (2<<12)
#define CSR3_CLK_16           (3<<12)
#define CSR3_CLK_1            (4<<12)
#define CSR3                  (7<<12)

#define CSR2_CLK_2            (0<<8)
#define CSR2_CLK_4            (1<<8)
#define CSR2_CLK_8            (2<<8)
#define CSR2_CLK_16           (3<<8)
#define CSR2_CLK_1            (4<<8)
#define CSR2                  (7<<8)

#define CSR1_CLK_2            (0<<4)
#define CSR1_CLK_4            (1<<4)
#define CSR1_CLK_8            (2<<4)
#define CSR1_CLK_16           (3<<4)
#define CSR1_CLK_1            (4<<4)
#define CSR1                  (7<<4)

#define CSR0_CLK_2            (0)
#define CSR0_CLK_4            (1)
#define CSR0_CLK_8            (2)
#define CSR0_CLK_16           (3)
#define CSR0_CLK_1            (4)
#define CSR0                  (7)

/* 10. PWM CSR47 register */
#define CSR7_CLK_2            (0<<12)
#define CSR7_CLK_4            (1<<12)
#define CSR7_CLK_8            (2<<12)
#define CSR7_CLK_16           (3<<12)
#define CSR7_CLK_1            (4<<12)
#define CSR7                  (7<<12)

#define CSR6_CLK_2            (0<<8)
#define CSR6_CLK_4            (1<<8)
#define CSR6_CLK_8            (2<<8)
#define CSR6_CLK_16           (3<<8)
#define CSR6_CLK_1            (4<<8)
#define CSR6                  (7<<8)

#define CSR5_CLK_2            (0<<4)
#define CSR5_CLK_4            (1<<4)
#define CSR5_CLK_8            (2<<4)
#define CSR5_CLK_16           (3<<4)
#define CSR5_CLK_1            (4<<4)
#define CSR5                  (7<<4)

#define CSR4_CLK_2            (0)
#define CSR4_CLK_4            (1)
#define CSR4_CLK_8            (2)
#define CSR4_CLK_16           (3)
#define CSR4_CLK_1            (4)
#define CSR4                  (7)

/* 10. PWM PCR03 register */
#define CH3_AU_RL             (1<<27)
#define CH3_ONE_SHOT          ~(1<<27)
#define CH3INV_ON             (1<<26)
#define CH3EN                 (1<<24)
#define CH2_AU_RL             (1<<19)
#define CH2_ONE_SHOT          ~(1<<19)
#define CH2INV_ON             (1<<18)
#define CH2EN                 (1<<16)
#define CH1_AU_RL             (1<<11)
#define CH1_ONE_SHOT          ~(1<<11)
#define CH1INV_ON             (1<<10)
#define CH1EN                 (1<<8)
#define DZEN23                (1<<5)
#define DZEN01                (1<<4)
#define CH0_AU_RL             (1<<3)
#define CH0_ONE_SHOT          ~(1<<3)
#define CH0INV_ON             (1<<2)
#define CH0EN                 (1<<0)

/* 10. PWM PCR47 register */
#define CH7_AU_RL             (1<<27)
#define CH7_ONE_SHOT          ~(1<<27)
#define CH7INV_ON             (1<<26)
#define CH7EN                 (1<<24)
#define CH6_AU_RL             (1<<19)
#define CH6_ONE_SHOT          ~(1<<19)
#define CH6INV_ON             (1<<18)
#define CH6EN                 (1<<16)
#define CH5_AU_RL             (1<<11)
#define CH5_ONE_SHOT          ~(1<<11)
#define CH5INV_ON             (1<<10)
#define CH5EN                 (1<<8)
#define DZEN67                (1<<5)
#define DZEN45                (1<<4)
#define CH4_AU_RL             (1<<3)
#define CH4_ONE_SHOT          ~(1<<3)
#define CH4INV_ON             (1<<2)
#define CH4EN                 (1<<0)

/* 10. PWM PIER03 register */
#define PWMIE3                (1<<3)
#define PWMIE2                (1<<2)
#define PWMIE1                (1<<1)
#define PWMIE0                (1<<0)

/* 10. PWM PIER47 register */
#define PWMIE7                (1<<3)
#define PWMIE6                (1<<2)
#define PWMIE5                (1<<1)
#define PWMIE4                (1<<0)

/* 10. PWM PIFR03 register */
#define PWMIF3                (1<<3)
#define PWMIF2                (1<<2)
#define PWMIF1                (1<<1)
#define PWMIF0                (1<<0)

/* 10. PWM PIFR47 register */
#define PWMIF7                (1<<3)
#define PWMIF6                (1<<2)
#define PWMIF5                (1<<1)
#define PWMIF4                (1<<0)

/* 10. PWM POE03 register */
#define PWM3_OE               (1<<3)
#define PWM2_OE               (1<<2)
#define PWM1_OE               (1<<1)
#define PWM0_OE               (1<<0)

/* 10. PWM POE47 register */
#define PWM7_OE               (1<<3)
#define PWM6_OE               (1<<2)
#define PWM5_OE               (1<<1)
#define PWM4_OE               (1<<0)

/* 10. PWM CCR01 register */
#define CFLRI1                (1<<23)	
#define CRLRI1                (1<<22)	
#define CAPIF1                (1<<20)	
#define CAPCH1EN              (1<<19)	
#define CFL_IE1               (1<<18)	
#define CRL_IE1               (1<<17)	
#define INV1_ON               (1<<16)	
#define CFLRI0                (1<<7)	
#define CRLRI0                (1<<6)	
#define CAPIF0                (1<<4)	
#define CAPCH0EN              (1<<3)	
#define CFL_IE0               (1<<2)	
#define CRL_IE0               (1<<1)	
#define INV0_ON               (1<<0)	

/* 10. PWM CCR23 register */
#define CFLRI3                (1<<23)	
#define CRLRI3                (1<<22)	
#define CAPIF3                (1<<20)	
#define CAPCH3EN              (1<<19)	
#define CFL_IE3               (1<<18)	
#define CRL_IE3               (1<<17)	
#define INV3_ON               (1<<16)	
#define CFLRI2                (1<<7)	
#define CRLRI2                (1<<6)	
#define CAPIF2                (1<<4)	
#define CAPCH2EN              (1<<3)	
#define CFL_IE2               (1<<2)	
#define CRL_IE2               (1<<1)	
#define INV2_ON               (1<<0)

/* 10. PWM CCR45 register */
#define CFLRI5                (1<<23)	
#define CRLRI5                (1<<22)	
#define CAPIF5                (1<<20)	
#define CAPCH5EN              (1<<19)	
#define CFL_IE5               (1<<18)	
#define CRL_IE5               (1<<17)	
#define INV5_ON               (1<<16)	
#define CFLRI4                (1<<7)	
#define CRLRI4                (1<<6)	
#define CAPIF4                (1<<4)	
#define CAPCH4EN              (1<<3)	
#define CFL_IE4               (1<<2)	
#define CRL_IE4               (1<<1)	
#define INV4_ON               (1<<0)

/* 10. PWM CCR67 register */
#define CFLRI7                (1<<23)	
#define CRLRI7                (1<<22)	
#define CAPIF7                (1<<20)	
#define CAPCH7EN              (1<<19)	
#define CFL_IE7               (1<<18)	
#define CRL_IE7               (1<<17)	
#define INV7_ON               (1<<16)	
#define CFLRI6                (1<<7)	
#define CRLRI6                (1<<6)	
#define CAPIF6                (1<<4)	
#define CAPCH6EN              (1<<3)	
#define CFL_IE6               (1<<2)	
#define CRL_IE6               (1<<1)	
#define INV6_ON               (1<<0)

/* 10. PWM CAPENR03 register */
#define CAPCH3_ON             (1<<3)
#define CAPCH2_ON             (1<<2)
#define CAPCH1_ON             (1<<1)
#define CAPCH0_ON             (1<<0)

/* 10. PWM CAPENR47 register */
#define CAPCH7_ON             (1<<3)
#define CAPCH6_ON             (1<<2)
#define CAPCH5_ON             (1<<1)
#define CAPCH4_ON             (1<<0)

/* 11. SPI SPI_CNTRL register */
#define TXFULL                (1<<27)
#define SPITXEMPTY            (1<<26)
#define RXFULL                (1<<25)
#define RXEMPTY               (1<<24)
#define VARCLK_EN             (1<<23) 
#define DUAL_FIFO             (1<<21)

#define NENDIAN_NSLEEP        (0<<19)
#define ENDIAN_SLEEP          (1<<19)
#define ENDIAN_NSLEEP         (2<<19)
#define NENDIAN_SLEEP         (3<<19)
#define REORDER               (3<<19)

#define SPI_MODE_SLAVE        (1<<18)
#define SPI_IE                (1<<17)
#define SPI_IF                (1<<16)

#define SLP_2CK               (0<<12)
#define SLP_3CK               (1<<12)
#define SLP_4CK               (2<<12)
#define SLP_5CK               (3<<12)
#define SLP_6CK               (4<<12)
#define SLP_7CK               (5<<12)
#define SLP_8CK               (6<<12)
#define SLP_9CK               (7<<12)
#define SLP_10CK              (8<<12)
#define SLP_11CK              (9<<12)
#define SLP_12CK              (10<<12)
#define SLP_13CK              (11<<12)
#define SLP_14CK              (12<<12)
#define SLP_15CK              (13<<12)
#define SLP_16CK              (14<<12)
#define SLP_17CK              (15<<12)
#define SLEEP                 (15<<12)

#define CLKP_IDLE_H           (1<<11)
#define LSB_FIRST             (1<<10)
#define TX_NUM_TWO            (1<<8)
#define TX_NUM_ONE            ~(1<<8)

#define LEN_32BIT             (0<<3)
#define LEN_1BIT              (1<<3)
#define LEN_2BIT              (2<<3)
#define LEN_3BIT              (3<<3)
#define LEN_4BIT              (4<<3)
#define LEN_5BIT              (5<<3)
#define LEN_6BIT              (6<<3)
#define LEN_7BIT              (7<<3)
#define LEN_8BIT              (8<<3)
#define LEN_9BIT              (9<<3)
#define LEN_10BIT             (10<<3)
#define LEN_11BIT             (11<<3)
#define LEN_12BIT             (12<<3)
#define LEN_13BIT             (13<<3)
#define LEN_14BIT             (14<<3)
#define LEN_15BIT             (15<<3)
#define LEN_16BIT             (16<<3)
#define LEN_17BIT             (17<<3)
#define LEN_18BIT             (18<<3)
#define LEN_19BIT             (19<<3)
#define LEN_20BIT             (20<<3)
#define LEN_21BIT             (21<<3)
#define LEN_22BIT             (22<<3)
#define LEN_23BIT             (23<<3)
#define LEN_24BIT             (24<<3)
#define LEN_25BIT             (25<<3)
#define LEN_26BIT             (26<<3)
#define LEN_27BIT             (27<<3)
#define LEN_28BIT             (28<<3)
#define LEN_29BIT             (29<<3)
#define LEN_30BIT             (30<<3)
#define LEN_31BIT             (31<<3)
#define TX_BIT_LEN            (31<<3)

#define TX_NEG_F              (1<<2)
#define RX_NEG_F              (1<<1)
#define GO_BUSY               (1<<0)

/* 11. SPI SPI_SSR register */
#define LTRIG_F               (1<<5)
#define LTRIG_LEV             (1<<4)
#define LTRIG_EDG             ~(1<<4)
#define ASS_AUTO              (1<<3)
#define LVL_H                 (1<<2)
#define SSR_ACT               (1<<0)

/* 12. TIMER TCSR register */
#define CEN                   (1<<30)
#define TMR_IE                (1<<29)

#define MODE_ONE_SHOT         (0<<27)
#define MODE_PERIOD           (1<<27)
#define MODE_CONTINUE         (3<<27)
#define TMR_MODE              (3<<27)

#define CRST                  (1<<26)
#define CACT                  (1<<25)
#define TDR_EN                (1<<16)

/* 12. TIMER TISR register */
#define TMR_TIF               (1<<0)

/* 13. WATCHDOG WTCR register */
#define TO_2T4_CK             (0<<8)
#define TO_2T6_CK             (1<<8)
#define TO_2T8_CK             (2<<8)
#define TO_2T10_CK            (3<<8)
#define TO_2T12_CK            (4<<8)
#define TO_2T14_CK            (5<<8)
#define TO_2T16_CK            (6<<8)
#define TO_2T18_CK            (7<<8)
#define WTIS                  (7<<8)

#define WTE                   (1<<7)
#define WTIE                  (1<<6)
#define WTWKF                 (1<<5)
#define WTWKE                 (1<<4)
#define WTIF                  (1<<3)
#define WTRF                  (1<<2)
#define WTRE                  (1<<1)
#define CLRWTR                (1<<0)

/* 14 UART UA_IER register */
#define AUTO_CTS_EN           (1<<13)
#define AUTO_RTS_EN           (1<<12)
#define TIME_OUT_EN           (1<<11)
#define WAKE_EN               (1<<6)
#define BUF_ERR_IEN           (1<<5)
#define RTO_IEN               (1<<4)
#define MODEM_IEN             (1<<3)
#define RLS_IEN               (1<<2)
#define THRE_IEN              (1<<1)
#define RDA_IEN               (1<<0)

/* 14 UART UA_FCR register */
#define RTS_TRI_1             (0<<16)
#define RTS_TRI_4             (1<<16)
#define RTS_TRI_8             (2<<16)
#define RTS_TRI_14            (3<<16)
#define RTS_TRI_30_14         (4<<16)
#define RTS_TRI_46_14         (5<<16)
#define RTS_TRI_62_14         (6<<16)
#define RTS_TRI_LEV           (15<<16)

#define RX_DIS                (1<<8)

#define RFITL_1               (0<<4)
#define RFITL_4               (1<<4)
#define RFITL_8               (2<<4)
#define RFITL_14              (3<<4)
#define RFITL_30_14           (4<<4)
#define RFITL_46_14           (5<<4)
#define RFITL_62_14           (6<<4)
#define RFITL                 (15<<4)

#define TX_RST                (1<<2)
#define RX_RST                (1<<1)

/* 14. UART UA_LCR register */
#define BCB                   (1<<6)
#define SPE                   (1<<5)
#define EPE                   (1<<4)
#define PBE                   (1<<3)
#define NSB_ONE_HALF          (1<<2)
#define NSB_ONE               ~(1<<2)

#define WL_5BIT               (0)
#define WL_6BIT               (1)
#define WL_7BIT               (2)
#define WL_8BIT               (3)
#define WLS                   (3)

/* 14. UART UA_MCR register */
#define RTS_ST                (1<<13)
#define LEV_RTS_H             (1<<9)
#define RTS                   (1<<1)

/* 14. UART UA_MSR register */
#define LEV_CTS_H             (1<<8)
#define CTS_ST                (1<<4)
#define DCTSF                 (1<<0)

/* 14. UART UA_FSR register */
#define TE_FLAG               (1<<28)
#define TX_OVER_IF            (1<<24)
#define TX_FULL               (1<<23)
#define TX_EMPTY              (1<<22)
#define RX_FULL               (1<<15)
#define RX_EMPTY              (1<<14)
#define BIF                   (1<<6)
#define FEF                   (1<<5)
#define PEF                   (1<<4)
#define RS485_ADD_DE          (1<<3)
#define RX_OVER_IF            (1<<0)

/* 14. UART UA_ISR register */
#define BUFERR_INT            (1<<13)
#define TOUT_INT              (1<<12)
#define MODEM_INT             (1<<11)
#define RLS_INT               (1<<10)
#define THRE_INT              (1<<9)
#define RDA_INT               (1<<8)
#define BUFERR_IF             (1<<5)
#define TOUT_IF               (1<<4)
#define MODEM_IF              (1<<3)
#define RLS_IF                (1<<2)
#define THRE_IF               (1<<1)
#define RDA_IF                (1<<0)

/* 14. UART UA_BAUD register */
#define DIV_X_EN              (1<<29)
#define DIV_X_ONE             (1<<28)

/* 14. UART UA_IRCR register */
#define INV_RX                (1<<6)
#define INV_TX                (1<<5)
#define LB                    (1<<2)
#define IrDA_TX               (1<<1)
#define IrDA_RX               ~(1<<1)

/* 14. UART UA_RS485_CSR register */
#define RS485_ADD_EN          (1<<15)
#define RS485_AUD             (1<<10)
#define RS485_AAD             (1<<9)
#define RS485_NMM             (1<<8)
							  
/* 14. UART UA_FUN_SEL register */
#define UART_EN               (0)
#define IrDA_EN               (2)
#define RS485_EN              (3)
#define FUN_SEL               (3)

/* 15. ADC ADDR0~7 register */
#define VALID                 (1<<17)
#define OVERRUN               (1<<16)

/* 15. ADC ADCR register */
#define ADST                  (1<<11)
#define DIFFEN                (1<<10)
#define TRGE_EN               (1<<8)

#define TRG_LEV_L             (0<<6)
#define TRG_LEV_H             (1<<6)
#define TRG_EDG_F             (2<<6)
#define TRG_EDG_R             (3<<6)
#define TRG_COND              (3<<6)

#define TRGS_STADCP           (0<<4)
#define TRGS                  (3<<4)

#define MD_SIG                (0<<2)
#define MD_BURST              (1<<2)
#define MD_SIG_SCN            (2<<2)
#define MD_CON_SCN            (3<<2)
#define ADMD                  (3<<2)

#define ADIE                  (1<<1)
#define ADEN                  (1<<0)

/* 15. ADC ADCHER register */
#define CH7_ADC7              (0<<8)
#define CH7_VBGI              (1<<8)
#define CH7_MODE              (3<<8)

#define CHEN7                 (1<<7)
#define CHEN6                 (1<<6)
#define CHEN5                 (1<<5)
#define CHEN4                 (1<<4)
#define CHEN3                 (1<<3)
#define CHEN2                 (1<<2)
#define CHEN1                 (1<<1)
#define CHEN0                 (1<<0)

/* 15. ADC ADCMPR01 register */
#define CMPCH0                (0<<3)
#define CMPCH1                (1<<3)
#define CMPCH2                (2<<3)
#define CMPCH3                (3<<3)
#define CMPCH4                (4<<3)
#define CMPCH5                (5<<3)
#define CMPCH6                (6<<3)
#define CMPCH7                (7<<3)
#define CMPCH                 (7<<3)

#define CMP_GE                (1<<2)
#define CMP_LESS              ~(1<<2)
#define ADC_CMPIE             (1<<1)
#define ADC_CMPEN             (1<<0)

/* 15. ADC ADSR register */	  
#define ADC_BUSY              (1<<3)
#define ADC_CMPF1             (1<<2)
#define ADC_CMPF0             (1<<1)
#define ADF                   (1<<0)

/* 15. ADC ADCALR register */
#define CALDONE               (1<<1)
#define CALEN                 (1<<0)

/* 16. EBI EBICON register */
#define HCLK_1                (0<<8)
#define HCLK_2                (1<<8)
#define HCLK_4                (2<<8)
#define HCLK_8                (3<<8)
#define HCLK_16               (4<<8)
#define HCLK_32               (5<<8)
#define MCLKDIV               (7<<8)

#define EXTBW16               (1<<1)
#define EXTBW8                ~(1<<1)
#define EXTEN                 (1<<0)

/* 17.FMC ISPCON register */
#define ET_20MS               (0<<12)
#define ET_25MS               (1<<12)
#define ET_30MS               (2<<12)
#define ET_35MS               (3<<12)
#define ET_3MS                (4<<12)
#define ET_5MS                (5<<12)
#define ET_10MS               (6<<12)
#define ET_15MS               (7<<12)
#define ET                    (7<<12)

#define PT_40US               (0<<8)
#define PT_45US               (1<<8)
#define PT_50US               (2<<8)
#define PT_55US               (3<<8)
#define PT_20US               (4<<8)
#define PT_25US               (5<<8)
#define PT_30US               (6<<8)
#define PT_35US               (7<<8)
#define PT                    (7<<8)

#define SWRST                 (1<<7)
#define ISPFF                 (1<<6)
#define LDUEN                 (1<<5)
#define CFGUEN                (1<<4)
#define BS_LD                 (1<<1)
#define BS_AP                 ~(1<<1)
#define ISPEN                 (1<<0)

/* 17.FMC ISPCMD register */
#define READ                  (0)
#define READ_CID              (0x0B)
#define READ_DID              (0x0C)
#define PROGRAM               (0x21)
#define PAGE_ERASE            (0x22)
#define STANDBY               (0x30)
#define COMMAND               (0x3F)

/* 17.FMC ISPTRG register */
#define ISPGO                 (1<<0)

/* 17.FMC FATCON register */
#define L_SPEED               (1<<4)

#define FATS_40NS             (0<<1)
#define FATS_50NS             (1<<1)
#define FATS_60NS             (2<<1)
#define FATS_70NS             (3<<1)
#define FATS_80NS             (4<<1)
#define FATS_90NS             (5<<1)
#define FATS_100NS            (6<<1)
#define FATS                  (7<<1)

#define FPSEN                 (1<<0)

/* 18.ACMP ACMP_CR register */
#define ACMPOINV				(1<<6)
#define NEGSEL					(1<<4)
#define HYSEN					(1<<2)
#define ACMPIE					(1<<1)
#define ACMPEN					(1<<0)

#endif
